Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
VLSI array processors
The algebraic eigenvalue problem
The algebraic eigenvalue problem
SIAM Journal on Scientific and Statistical Computing
On the convergence of the cyclic Jacobi method for parallel block orderings
SIAM Journal on Matrix Analysis and Applications
Matrix computations (3rd ed.)
Supporting systolic and memory communication in iWarp
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Introduction to VLSI Systems
Architecture of the PSC-a programmable systolic chip
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
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Describes and analyzes the Hybrid Array Ring Processor (HARP) architecture. The HARP is an application specific architecture built around a host processor, shared memory, and a set of memory mapped processing cells that are connected both into an open backplane and a bidirectional systolic ring. The architecture is analyzed through detailed simulation of a system implementation based on the Texas Instruments TMS34082 floating point RISC. A bus controller is designed that provides a tightly coupled DMA function that accelerates systolic communication and supports new interleaved transparent communications and reduced overhead message passing. The architecture is benchmarked with the matrix multiplication, FFT, QRD, and SVD algorithms.