VLSI array processors
Systolic Parallel Processing
Enhanced channel estimation using superimposed training based on universal basis expansion
IEEE Transactions on Signal Processing
Handbook on Array Processing and Sensor Networks
Handbook on Array Processing and Sensor Networks
Architecture Based on Array Processors for Data-Dependent Superimposed Training Channel Estimation
RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
Channel estimation using implicit training
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
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In this paper, a configurable superimposed training (ST)/data-dependent ST (DDST) transmitter and architecture based on array processors (APs) for DDST channel estimation are presented. Both architectures, designed under full-hardware paradigm, were described using Verilog HDL, targeted in Xilinx Virtex-5 and they were compared with existent approaches. The synthesis results showed a FPGA slice consumption of 1% for the transmitter and 3% for the estimator with 160 and 115MHz operating frequencies, respectively. The signal-to-quantization-noise ratio (SQNR) performance of the transmitter is about 82 dB to support 4/16/64-QAM modulation. A Monte Carlo simulation demonstrates that the mean square error (MSE) of the channel estimator implemented in hardware is practically the same as the one obtained with the floating-point golden model. The high performance and reduced hardware of the proposed architectures lead to the conclusion that the DDST concept can be applied in current communications standards.