A new 2-D systolic digital filter architecture without global broadcast

Authors:
Lan-Da Van
Affiliations:
Chip Implementation Center (CIC), National Science Council, Hsinchu 300, Taiwan, R.O.C.
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2002

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Abstract

In this paper, we propose two-dimensional (2-D) systolic-array infinite-impulse response (IIR) and finite-impulse response (FIR) digital filter architectures without global broadcast, by the hybrid of a modified reordering scheme and a new systolic transformation. This architecture has local broadcast, lower-quantization error, and zero latency without sacrificing the number of multipliers, as well as delay elements under the satisfactory critical period. Furthermore, we extend this new architecture to a useful 2-D systolic cascade-form architecture and provide the comprehensive error analysis for the proposed architectures.