VLSI array processors
Parallel processing architectures and VLSI hardware: vol. 1
Parallel processing architectures and VLSI hardware: vol. 1
Parallel computation: models and methods
Parallel computation: models and methods
Parallel Processing: From Applications to Systems
Parallel Processing: From Applications to Systems
Computer
Determining objective functions in systolic array designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Author is discussing a problems of determining parameters suitable systolic arrays for implementation regular 3-nested loop algorithms. Author shows that if the characteristics of so called adaptable algorithms to the projection direction are used we have the best results. This characteristics can be space (number of processor elements, chip area, input-output elements,...), time (flow period of processor, summary time of algorithm realization,...) or one combination of those and the subject of interesting in this paper is one from them - number of processor elements. In this paper is given transformation matrix, which maps the given index space in another index space and reduces the number of processing elements in the systolic array. Obtained results in this paper are illustrated on the example of matrix-matrix multiplication algorithm as one typical adaptable algorithm and that on the examples of both possibly synthesized systolic arrays of them i.e. planar and non-planar type systolic arrays.