Determining objective functions in systolic array designs

Authors:
C. N. Zhang;J. H. Weston;Y.-F. Yan
Affiliations:
Department of Computer Science, University of Regina, Regina, Canada;Department of Mathematics and Statistics, University of Regina, Regina, Canada;Department of Computer Science, University of Regina, Regina, Canada
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1994

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Abstract

The space-time mapping of the dependency matrix of an algorithm may be used to study proposed systolic array implementations. In this paper we consider nested loop structures and use the space-time mapping approach to examine six objective functions, processor pipelining rate, computation time, throughput, number of processing elements, geometric area and space utilization. An elementary expression for each of these objective functions is derived which depends only on the space-time transformation and the size of loops. Moreover, several necessary and sufficient conditions for optimizing individual objective function are provided.