Discrete-time signal processing
Discrete-time signal processing
Efficient realizations of analysis and synthesis filters based on the 2-D discrete wavelet transform
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
A new, fast, and efficient image codec based on set partitioning in hierarchical trees
IEEE Transactions on Circuits and Systems for Video Technology
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Journal of VLSI Signal Processing Systems
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This paper presents architectures and scheduling algorithms for the 2-D Discrete Wavelet Transform (DWT) and the Inverse Discrete Wavelet Transform (IDWT) using 9/7-tap filter banks based on the Non-expansive Symmetric Extension (NSE) scheme that reduces distortion at boundaries of reconstructed image. The hardware has been implemented for image blocks of size 32 x 32 pixels, up to third level of transform and cuts down the power consumption at architecture level by incorporating three techniques, viz., Canonic Sign Digit (CSD) and common sub-expression sharing technique, Gray code addressing mode and resource sharing. The implementation has been tested using 0.35 um (three metal) technology by simulation at functional, circuit and physical levels. The performance measures of implementation, viz., area, memory requirement, speed and power have been evaluated.