Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters

Authors:
Tze-Yun Sung;Yaw-Shih Shieh;Chun-Wang Yu;Hsi-Chin Hsin
Affiliations:
Chung Hua University, Taiwan;Chung Hua University, Taiwan;Chung Hua University, Taiwan;National Formosa University, Taiwan
Venue:
PDCAT '06 Proceedings of the Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies
Year:
2006

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Abstract

This paper proposes two architectures of 2-D discrete wavelet transform (DWT) and inverse DWT (IDWT). The first high-efficiency architecture comprises a transform module, an address sequencer, and a RAM module. The transform module has uniform and regular structure, simple control flow, and local communication. The significant advantages of the single transform module are full hardware-utilization and low-power. The second architecture features parallel and pipelined computation and high throughput. Both architectures are very suitable for VLSI implementation of new-generation image coding/decoding systems, such as JPEG-2000. In the realization of 2-D DWT/IDWT, we focus on a FPGA and VLSI implementation using 4-tap Daubechies filters, which saves power and reduces chip area.