JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures
JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures
Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters
PDCAT '06 Proceedings of the Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies
Implementing a new architecture of wavelet packet transform on FPGA
AMTA'07 Proceedings of the 8th WSEAS international conference on Acoustics & music: theory & applications
Low-power and high-performance 2-D DWT and IDWT architectures based on 4-tap Daubechies filters
MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
Reconfigurable VLSI architecture for FFT processor
WSEAS Transactions on Circuits and Systems
Reconfigurable architecture for VLSI 9/7-5/3 wavelet filter
IMCAS'10 Proceedings of the 9th WSEAS international conference on Instrumentation, measurement, circuits and systems
Two fast architectures for the direct 2-D discrete wavelettransform
IEEE Transactions on Signal Processing
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In this paper, the high-efficient and reconfigurable architectures for the 9/7-5/3 discrete wavelet transform (DWT) based on convolution scheme are proposed. The proposed parallel and pipelined architectures consist of a high-pass filter (HF) and a low-pass filter (LF). The critical paths of the proposed architectures are reduced. Filter coefficients of the biorthogonal 9/7-5/3 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architectures, all multiplications are performed using less shifts and additions. The proposed reconfigurable architecture is 100% hardware utilization and ultra low-power. The proposed reconfigurable architectures have regular structure, simple control flow, high throughput and high scalability. Thus, they are very suitable for new-generation image compression systems, such as JPEG-2000.