Non-Memory-Based and Real-Time Zerotree Building for Wavelet Zerotree Coding Systems
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
An Efficient Architecture for a Lifted 2D Biorthogonal DWT
Journal of VLSI Signal Processing Systems
A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform
Journal of Signal Processing Systems
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We present a VLSI architecture for the separable two-dimensional discrete wavelet transform (DWT) decomposition. Using a computation-schedule table, we show how the proposed separable architecture uses only a minimal number of filters to generate all levels of DWT computations in real time. For the computation of an N×N 2-D DWT with a filter length L, this architecture spends around N2 clock cycles, and requires 2NL-2N storage units, 3L multipliers, as well as 3(L-1) adders