A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Memory Efficient 3-D DWT Architecture
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
IEEE Transactions on Signal Processing
Design and implementation of an RNS-based 2-D DWT processor
IEEE Transactions on Consumer Electronics
Low memory and low complexity VLSI implementation of JPEG2000 codec
IEEE Transactions on Consumer Electronics
A novel VLSI architecture for multidimensional discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology
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The implementation of the memory for storing image and transform coefficients in 2-D DWT processing systems using the more cost-effective external memory module such as DDR DRAM is shown to suffer from effective memory bandwidth which is significantly lower than the memory system peak bandwidth if the conventional direct logical-to-physical memory address mapping is adopted. The low effective memory bandwidth is caused by the high level of memory overhead cycle occurrence which is in turn is closely related to the logical memory access patterns of 2-D DWT processes. The problem becomes even more severe for the 2-D DWT processing of video. An analysis on the logical memory access patterns of multi-level 2-D DWT is carried out and an enhanced logical-to-physical memory mapping scheme which minimizes the occurrence of memory overhead cycles is proposed. The proposed scheme is simulated and its performance in terms of effective memory access bandwidth is evaluated and compared with the conventional direct mapping scheme.