A Memory Efficient 3-D DWT Architecture

Authors:
B. Das;Swapna Banerjee
Affiliations:
-;-
Venue:
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Year:
2003

Citing 7
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Abstract

This paper proposes a memory efficientreal-time 3-D DWT algorithm and its architectural implementation. As the running JD-DWT refreshes the wavelet coefficients with the arrival of every two newframes, the latency of the conventional 3D-DWT reduces by at least 录 times. For realization of the transform canonical signeddigit multiplier has been used. Parallelismbeing an added advantage for fast processing has been used with three pipelinedstages in this architecture. For coefficientmapping, correlation between LPF andHPF in orthogonal Daubechies wavelet filter has been used. In this design the mem-ory requirement has been optimized to theorder O(KN2 + (K - 2) x N). The proposed architecture has been implementedon Xilinx FPGA devices at an operatingfrequency of 75MHz. This low complex architecture ensures 100% hardware utilization.