Energy recovery for the design of high-speed, low-power static RAMs
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
A new CMAC neural network architecture and its ASIC realization
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
The design and implementation of a power efficient embedded SRAM
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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The newly proposed SRAM performs both read and write operations in the current-mode. Due to the current-mode operations, voltage swings at bit-lines and data-lines are kept very small during read and write. The AC power dissipation of bit-lines and data-lines can thus be saved efficiently. For an embedded SRAM macro used in an 8-bit µ-controller, the SRAM using the fully current-mode technique consumes only 30% power dissipation as compared to the SRAM with only current-mode read operation. Experimental results show good agreement with the simulation results and prove the feasibility of the new technique.