The design and implementation of a power efficient embedded SRAM

Authors:
Yijun Liu;Pinghua Chen;Wenyan Wang;Zhenkun Li
Affiliations:
The Faculty of Computer, Guangdong University of Technology, Guangdong, China;The Faculty of Computer, Guangdong University of Technology, Guangdong, China;The Faculty of Computer, Guangdong University of Technology, Guangdong, China;The Faculty of Computer, Guangdong University of Technology, Guangdong, China
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

In this paper, a power efficient 2K asynchronous SRAM is presented for embedded applications. The SRAM adopts a low swing write scheme, which greatly reduces the power dissipated by charging and discharging the bitlines. A small dual-rail decoder is proposed to compensate for the extra silicon area needed by the low swing write technique. The new SRAM is demonstrated to a factor of 4 improvement in power efficiency over a commercial SRAM macro. It also 30% faster than the commercial SRAM macro with only 3% area overhead