IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
A Low-Power High-Performance Embedded SRAM Macrocell
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
A 500-MHz low-power five-port CMOS register file
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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This paper presents a new approach for energy reduction and speedimprovement of multiport SRAMs. The key idea is to use current-modefor both read and write operations. To toggle a memory cell,a very small voltage swing is first created on the high-capacitivebit lines. This voltage is then translated into a differentialcurrent being injected into the cell, which in turn allowscomplementary potential to be developed on the cell nodes. Ascompared to the conventinal write approach, spice simulations usinga 0.35-μm CMOS process have shown 2.8 to 9.9× in energysavings and 1.02 to 6.36 × reduction in delay, for memorysizes of 32 to 1 K words. We also present a current-modesense-amplifier that operates in a similar fashion as the writecircuit. The design and implementation of a pipelined 32 × 64three-port register file utilizing the proposed technique isdescribed. Measurements of the register file chip have confirmedthe feasibility of this approach.