PixelFlow: high-speed rendering using image composition
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
Low Power Digital CMOS Design
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
Design of an on-chip reflectance map
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
Design of a fast voxel processor for parallel volume visualization
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
Super resolution volume rendering hardware
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
Towards a scalable architecture for real-time volume rendering
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
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The amount of energy consumed in basic CMOS building blocks, like external RAM, external bus-structures, multipliers, local (cache) memory and on chip bus-structures, is analyzed thoroughly to find ways for substantial improvement of the power consumption of high speed graphics algorithms. A Field Programmable Function Array capable of low-power execution of a wide range of algorithms is introduced. Aspects of the compilation of the volume rendering algorithm to this architecture are discussed.