Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Proceedings of the 43rd annual Design Automation Conference
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
CMOS/nano co-design for crossbar-based molecular electronic systems
IEEE Transactions on Nanotechnology
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories
IEEE Transactions on Nanotechnology
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In this paper we propose two efficient repair techniques for hybrid nano/CMOS architecture to provide high level of defect tolerance at a modest cost. We have applied the proposed techniques to a lookup table(LUT) based Boolean logic approach. The proposed repair techniques are efficient in utilization of spare units and viable for various Boolean logic implementations. We show that the proposed techniques are capable of handling upto 20% defect ratess in hybrid nano/CMOS architecture and upto 14% defect rates for large ISCAS'85 benchmark circuits synthesized into smaller sized LUTs.