PixelFlow: high-speed rendering using image composition
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
Low Power Digital CMOS Design
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
Design of an on-chip reflectance map
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
Design of a fast voxel processor for parallel volume visualization
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
Super resolution volume rendering hardware
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
Towards a scalable architecture for real-time volume rendering
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
Design principles of hardware-based phong shading and bump mapping
EGGH'96 Proceedings of the Eleventh Eurographics conference on Graphics Hardware
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A theory about the energy consumption of algorithms realized in CMOS, presented in related work, makes it possible to calculate the minimal amount of energy dissipated for the execution of an algorithm. The rendering of a dense dataset with three variants of the Volume Rendering algorithm with be considered as an example of the methodology. The absolute lower bound of the energy consumption is calculated for the rendering ofa dense 256^3 dataset using implementations of the algorithms in an 1µm CMOS process. Predictions of the energy consumption in future CMOS generations are given as well.