Algorithms for multilevel logic optimization
Algorithms for multilevel logic optimization
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Logic extraction and factorization for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Node normalization and decomposition in low power technology mapping
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Power-aware FPGA logic synthesis using binary decision diagrams
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
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This paper describes algebraic techniques that target low power consumption. A unique power cost function based on de-composed factored form representation of a Boolean expression is introduced to guide the structural transformations. Circuits synthesized by the SIS and POSE consume 54.5% and 10.4% more power than that obtained by our tool respectively.