An optimization-based error calculation for statistical power estimation of CMOS logic circuits

Authors:
Byunggyu Kwak;Eun Sei Park
Affiliations:
Samsung Data Systems, Seoul, 135-080, Korea;School of Electrical and Computer Engineering, Hanyang University, Ansan, 425-791 Korea
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

Citing 6
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Abstract

In this paper, we present a statistical power estimation method where estimation time and accuracy can be balanced by assigning smaller errors to the nodes with higher power dissipation and higher errors to the nodes with lower power dissipation. To calculate the error rates for individual nodes, a quadratic programming based problem will be formulated which incorporates the distribution data of all individual node switching activities. Also, an iterative statistical power estimation system will be presented. Finally, we will demonstrate experimental results which show drastic reduction in the number of simulation patterns compared to previous methods.