Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPC(tm) Microprocessor

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Venue:
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Year:
2000

Citing 3
Cited 1

A survey of power estimation techniques in VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Design and analysis of power distribution networks in PowerPC microprocessors

DAC '98 Proceedings of the 35th annual Design Automation Conference
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

Circuit power estimation using pattern recognition techniques

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

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Abstract

With increasing operating frequency and high packing density in start-of-the-art VLSI/ULSI design, power analysis is vital to ensure normal chip operation and better reliability. One of the most serious concerns because of high power is the dramatic on-chip temperature rise and the degraded chip performance. A CMOS digital circuit always consumes power no matter if it is switching or stable. Its four power consumption elements are: dynamic switch power, short-circuit power, internal power, and leakage power. Great deals of research efforts have been spent on the estimation of those power elements [1] [2] [3]. All four elements need to be estimated for the maximum accuracy in power analysis.