Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Application of GF(2p) CA in Burst Error Correcting Codes
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
GLFSR-a new test pattern generator for built-in-self-test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents an efficient BIST solution for VLSI circuit testing based on GF(2p) CA (Cellular automata on an extended Galois Field). The novel architecture of GF(2p)) CA permits the BIST structure to be highly customized to the circuit under test (CUT). A methodology has been proposed to optimize the design of GF(2p) CA structure to maximize the fault coverage in a given CUT. In addition, an innovative scheme based on logic folding is presented to reduce the BIST overhead and make it more effective for large circuits.