Multi-Modal Built-In Self-Test for Symmetric Microsystems
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On-Chip Pseudorandom MEMS Testing
Journal of Electronic Testing: Theory and Applications
Pseudorandom functional BIST for linear and nonlinear MEMS
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Electro-thermal Stimuli for MEMS Testing in FSBM Technology
Journal of Electronic Testing: Theory and Applications
Built-in-self-test techniques for MEMS
Microelectronics Journal
Yield analysis for self-repairable MEMS devices
Analog Integrated Circuits and Signal Processing
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Pseudorandom BIST for test and characterization of linear and nonlinear MEMS
Microelectronics Journal
A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
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A built-in self-test technique for MEMS that is applicable to symmetrical microstructures is described. A combination of existing layout features and additional circuitry is used to make measurements from symmetrically-locatedpoints. In addition to the normal sense output, self-test outputs are used to detect the presence of layout asymmetry that are caused by local, hard-to-detect defects. Simulation results for an accelerometer reveal that our self-test approach is able to distinguish misbehavior resulting from local defects and manufacturing process variations.