System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Built-in self-detection/correction architecture for motion estimation computing arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents simulations of 3 different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo-simulations. The simulations clearly favors the minority-3 Mirrored gate, and a gate-level ...