System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Enrichment of limited training sets in machine-learning-based analog/RF test
Proceedings of the Conference on Design, Automation and Test in Europe
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With proliferation in wireless applications, RFcircuitry is being included in a large number ofIntegrated Circuit (IC) designs. The testing of RFdevices has become increasingly expensive due to thehigh cost of RF testers as well as the test times for RFcircuits. The use of a new concurrent test methodologyreduces RF test time by measuring multiple RFparameters in parallel using modulated RF stimuli.Experimental results on a GaAs Low-Noise Amplifier(LNA) are described.