A building block BIST methodology for SOC designs: a case study

Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Power-aware SoC test planning for effective utilization of port-scalable testers

ACM Transactions on Design Automation of Electronic Systems (TODAES)

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Built-in self-detection/correction architecture for motion estimation computing arrays

IEEE Transactions on Very Large Scale Integration (VLSI) Systems