System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defect-based testing for memory concentrates on defect analysis of key parts of the layout and the development of application-independent patterns that will test for likely failures. Testing hundreds of embedded memories on today's SoC designs requires a combination of these approaches in order to assure high quality. Historically, DBT has been enabled in large vertically structured companies that included design, test development, and manufacturing. Many of today's SoCs are built with a different approach, the "customer-owned tooling" (COT) model, where a fables design customer builds a chip with third party IP, including memories, manufactures it through a foundry, and tests it at a separate test house. This complex supply chain cannot be ignored when developing a test solution.