Testing gigabit multilane SerDes interfaces with passive jitter injection filters
Authors:
Bernd Laquai;Yi Cai
Affiliations:
-;-
Venue:
Proceedings of the IEEE International Test Conference 2001
Year:
2001
Citing
0
Cited
1
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Quantified Score
Hi-index
0.00
Visualization
Abstract