System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
| Hi-index | 0.00 |
We have developed a partially rotational scan (PRS) register used for the n-detection BIST (built-in self-test) that can detect not only delay faults but also unmodeled faults. The developed circuit consists of a shift register with partial rotation. We also present a procedure for selecting test vectors from ATPG (automatic test pattern generation) ones. This testing method enables at-speed testing and the stuck-at fault coverage of n 脳 100%by using subset of the ATPG vectors. And it drastically reduces the number of vectors input from an external low-speed tester. Computer simulations of stuck-at fault coverage are conducted onISCAS'85, ISCAS'89, and ITC'99 circuits for detection times n of 1, 2, 3, 5, 10, and 15. They show that the compaction rates of the ATPG test vectors range from 52.4% (s713) to 0.9% (c499) of origin. This result demonstrates that the PRS register can accomplish low-cost, at-speed testing.