Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment

Authors:
Raimund Ubar;Tatjana Shchenova;Gert Jervan;Zebo Peng
Affiliations:
Tallinn University of Technology;Tallinn University of Technology;Linköping University;Linköping University
Venue:
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Year:
2005

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System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

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Abstract

An unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. ...