System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
| Hi-index | 0.00 |
Intelligent radio frequency (RF) front ends make use of MMIC and MEMS devices to provide a limited range of programmability to what have historically been fixed resistive, capacitive, and inductive impedance matching networks. Many BIST methods for mixed-signal systems can also be used to monitor and provide feedback for the control of such RF systems. For example, spectral techniques can be used to analyze and determine the center frequency of a bandpass filter. Information relative to the center frequency can then be fed back into the system, and adjustments can be made to fine tune the filter. In this paper we outline our spectral based, mixed-signal approach for monitoring the health of analog and RF components in mixed-signal systems on-chip. In our approach we use well known DSP techniques based on the FFT for on-chip signal generation and analysis. We reduce required hardware by using the same functional block to analyze analog output signals that we use to generate m tone stimulus signals. By providing on-chip functional test capability, we also reduce test time required in expensive ATE. Our techniques have been prototyped and demonstrated on a Xilinx Virtex-II FPGA using an off-chip ADC and DAC, and we are currently implementing the technique on an ASIC using a 0.13µm process with target execution speeds of 2-16GHz1.