Temperature-aware test scheduling for multiprocessor systems-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper presents simulations of 3 different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo-simulations. The simulations clearly favors the minority-3 Mirrored gate, and a gate-level ...