Alternate Loop-Back Diagnostic Tests for Wafer-Level Diagnosis of Modern Wireless Transceivers using Spectral Signatures

Authors:
Ganesh Srinivasan;Abhijit Chatterjee;Friedrich Taenzler
Affiliations:
Georgia Institute of Technology;Georgia Institute of Technology;Texas Instruments
Venue:
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Year:
2006

Citing 0
Cited 7

A Module for BiST of CMOS RF Receivers

Journal of Electronic Testing: Theory and Applications
Predictive test strategy for CMOS RF mixers

Integration, the VLSI Journal
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
An on-chip loopback block for RF transceiver built-in test

IEEE Transactions on Circuits and Systems II: Express Briefs
Detailed characterization of transceiver parameters through loop-back-based BiST

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Built-in loopback test for IC RF transceivers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ...