Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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In this paper we present new low-cost, digital compatible and efficient built-in test scheme for analog circuits. Using the proposed test methodology both catastrophic and parametric failures can be detected with very little on-chip hardware. The test methodology uses a vernier technique to digitize the response of the circuit-under-test (CUT) with the help of voltage comparator and simple reference waveform generator circuit. The digitized response is scanned out of the system using digital scan and analyzed externally for precise reconstruction of the response waveform. The specifications of the embedded analog circuit can be predicted accurately from the reconstructed waveform for making pass/fail decisions. Simulation results are presented.