System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On-chip source synchronous interface timing test scheme with calibration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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A majority of digital logic devices receives stimulus from an external system clock and sends information out on bus pins which are synchronized to the system clock. During functional testing of such devices, ATE architectures supply the clock and input data signals. The output signals generated by these devices are synchronous to the tester and are sampled accurately by the test equipment's strobe circuits. With the emergence of wide data busses in memories and high speed communication protocols implemented to transfer data between the CPU and peripherals, it has become necessary to forward a clock along with a group of bus pins to maintain skew across the high speed bus pins to an acceptable value for system design. This has resulted in a class of devices which have source synchronous busses where output signals are sent out relative to their strobe (output clock) signals. This paper describes the challenges associated with testing this class of devices with the classical automatic test equipment (ATE) architecture and presents a unique hardware solution implemented on a contemporary tester architecture to meet the test challenge. This paper also compares this implementation with other solutions available in the ATE domain.