System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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System-on-Chip (SoC) technologies are evolving towardsthe integration of highly heterogeneous devices, includinghardware of a different nature, such as digital, analogueand mixed-signal, together with software components.Embedding transducers, as predicted by technologyroadmaps, is yet another step in this continuous search forhigher levels of integration and miniaturisation. Embeddedtransducers fabricated with Silicon/CMOS compatibletechnologies may have a lower performance thantransducers fabricated with fully dedicated technologies.However, they offer the Industry the possibility ofproviding low cost applications for very large marketniches, while still keeping the required transducersensitivity. This is the case, for example, foraccelerometers or CMOS imagers. Test technology forSoC devices is rapidly maturing. Yet many difficulties stillremain, in particular for addressing the test of analogueand mixed-signal parts. Embedded transducers can beseen as analogue components. But given the fact that theywork with signals other than electrical, the test of theseparts is even harder to study. In this paper, we will presentour work in the field of MEMS testing and its evolutiontowards transducer on-chip testing.