Optimal Diagnosis Procedures for k-out-of-n Structures
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Loop-shaping H∞-control of a 2-DOF piezoelectric-stack actuated platform for nanoscale positioning
ICRA'09 Proceedings of the 2009 IEEE international conference on Robotics and Automation
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The authors describe a proprietary membrane probe card that addresses the needs of testing VLSI devices at the wafer level. The membrane probe allows the testing of devices with a high pin count at operating speed, while allowing a complete package test at the wafer level. The concepts and structure of the probe are examined, and its performance is demonstrated by time-domain and frequency-domain measurements of the typical electrical characteristics of a VLSI digital probe that accesses 272 pads at a pitch of 110 mu m. Applications to a bipolar ECL (emitter-coupled logic) flash A/D (analog-to-digital) converter, a bipolar ECL D/A converter, an application-specific CMOS IC, an NMOS VLSI central processing unit, and area-array solder bumps are presented.