Diagnosis and Repair of Memory with Coupling Faults
IEEE Transactions on Computers
Applied combinatorics (3rd ed.)
Applied combinatorics (3rd ed.)
Wafer-Level Testing with a Membrane Probe
IEEE Design & Test
Diagnosing double regular systems
Annals of Mathematics and Artificial Intelligence
Max-throughput for (conservative) k-of-n testing
ISAAC'11 Proceedings of the 22nd international conference on Algorithms and Computation
Sequential testing policies for complex systems under precedence constraints
Expert Systems with Applications: An International Journal
| Hi-index | 14.98 |
Diagnosis strategies are investigated for repairable VLSI and WSI structures based on integrated diagnosis and repair. Knowledge of the repair strategy, the probability of each unit being good, and the expected test time of each unit is used by the diagnosis algorithm to select units for testing. The general problem is described, followed by an examination of a specific case. For k-out-of-n structures, a complete proof is given for the optimal diagnosis procedure of Y. Ben-Dov (1981). A compact representation of the optimal diagnosis procedure is described, which requires O(n/sup 2/) space and can be generated in O(n/sup 2/) time. Simulation results are provided to show the improvement in diagnosis time over online repair and offline repair.