System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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The testable design and test of a software-controllable lab-on-a-chip, including a fluidic array of FlowFETs, control and interface electronics is presented. Test hardware is included for detecting faults in the DMOS electro-fluidic interface and the digital parts. Multi-domain fault modelling and simulation shows the effects of faults in the (combined) fluidic and electrical parts. Fault simulations also reveal important parameters of multi-domain test-stimuli for detecting both electrical and fluidic defects.