System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Wafer-level defect screening for "big-D/small-A" mixed-signal SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The subject of this paper is variance reduction and Nearest Neighbor Residual estimates forIDDQ and other continuous-valued test measurements. The key, new concept introduced is data-driven neighborhood identification about a die to reduce the variance of good and faulty IDDQ distributions. Using LSI Logic production data, neighborhood selection techniques are demonstrated. The main contribution of the paper isvariance reduction by the systematic use of the die location and wafer-or lot-level patterns andimproved identification of die outliers of continuous-valued test data such as IDDQ.