System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper presents a new method for measuring jitter tolerance of a SerDes receiver using the timing misalignment between the jittered source clock and the recovered clock. A sinusoidal jitter is injected into the serial bit stream. The method derives an equation for estimating BER accurately and is 10X faster than the conventional BER test method. The accuracy and test speed of the method are verified by 2.5 Gbps and 10 Gbps-SerDes experiments.