Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Generation and application of pseudorandom sequences for random testing
Generation and application of pseudorandom sequences for random testing
Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
Shift Register Sequences
Built-In TPG with Designed Phaseshifts
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
High Speed Ring Generators and Compactors of Test Data
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Application of High-Quality Built-In Test to Industrial Designs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Efficient Generation of Statistically Good Pseudonoise by Linearly Interconnected Shift Registers
IEEE Transactions on Computers
High Speed Generation of Maximal Length Sequences
IEEE Transactions on Computers
Toggle-Registers Generating in Parallel k kth Decimations of m-Sequences xP+ xk+ 1 Design Tables
IEEE Transactions on Computers
High-Speed M-Sequence Generators
IEEE Transactions on Computers
Automated synthesis of phase shifters for built-in self-test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High Performance Dense Ring Generators
IEEE Transactions on Computers
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The paper presents enhanced architectures of pseudo-randomtest pattern generators and on-chip test datadecompressors based on ring generators. The new structuresare aimed at improving their layout and routingproperties while at the same time reducing propagationdelays introduced by associated phase shifters.