Timing analysis in a logic synthesis environment
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Design and Synthesis of Self-Checking VLSI Circuits and Systems
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Logic Partitioning and Resynthesis for Testability
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Strongly Fault Secure Logic Networks
IEEE Transactions on Computers
Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration
IEEE Transactions on Computers
On Totally Self-Checking Checkers for Separable Codes
IEEE Transactions on Computers
A Theory of Totally Self-Checking System Design
IEEE Transactions on Computers
Error-Control Techniques for Logic Processors
IEEE Transactions on Computers
Resilient and adaptive performance logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Bergec code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN.