Communications of the ACM
Analog VLSI and neural systems
Analog VLSI and neural systems
VLSI analogs of neuronal visual processing: a synthesis of form and function
VLSI analogs of neuronal visual processing: a synthesis of form and function
A pulse-coded communications infrastructure for neuromorphic systems
Pulsed neural networks
An integrated vision sensor for the computation of optical flow singular points
Proceedings of the 1998 conference on Advances in neural information processing systems II
Computation of smooth optical flow in a feedback connected analog network
Proceedings of the 1998 conference on Advances in neural information processing systems II
Asynchronous Communication of 2D Motion Information UsingWinner-Takes-All Arbitration
Analog Integrated Circuits and Signal Processing
A VLSI Architecture for Modeling Intersegmental Coordination
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Multi-Chip Neuromorphic Motion Processing
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
A Throughput-On-Demand Address-Event Transmitter for Neuromorphic Chips
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
MICRONEURO '96 Proceedings of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems
A Reconfigurable Neuromorphic VLSI Multi-Chip System Applied to Visual Motion Computation
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
Retinomorphic Chips that see Quadrupple Images
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
Analog Integrated Circuits and Signal Processing
High fill-factor imagers for neuromorphic processing enabled by floating-gate circuits
EURASIP Journal on Applied Signal Processing
On the Advantages of Asynchronous Pixel Reading and Processing for High-Speed Motion Estimation
ISVC '08 Proceedings of the 4th International Symposium on Advances in Visual Computing
Multi-chip implementation of a biomimetic VLSI vision sensor based on the Adelson-Bergen algorithm
ICANN/ICONIP'03 Proceedings of the 2003 joint international conference on Artificial neural networks and neural information processing
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The extent of pixel-parallel focal plane image processing is limited by pixel area and imager fill factor. In this paper, we describe a novel multi-chip neuromorphic VLSI visual motion processing system which combines analog circuitry with an asynchronous digital interchip communications protocol to allow more complex pixel-parallel motion processing than is possible in the focal plane. This multi-chip system retains the primary advantages of focal plane neuromorphic image processors: low-power consumption, continuous-time operation, and small size. The two basic VLSI building blocks are a photosensitive sender chip which incorporates a 2D imager array and transmits the position of moving spatial edges, and a receiver chip which computes a 2D optical flow vector field from the edge information. The elementary two-chip motion processing system consisting of a single sender and receiver is first characterized. Subsequently, two three-chip motion processing systems are described. The first three-chip system uses two sender chips to compute the presence of motion only at a particular stereoscopic depth from the imagers. The second three-chip system uses two receivers to simultaneously compute a linear and polar topographic mapping of the image plane, resulting in information about image translation, rotation, and expansion. These three-chip systems demonstrate the modularity and flexibility of the multi-chip neuromorphic approach.