Single-Chip Stereo Imager

Authors:
Ralf M. Philipp;Ralph Etienne-Cummings
Affiliations:
Department of Electrical & Computer Engineering, Johns Hopkins University, Baltimore, MD, USA. rphilipp@jhu.edu;Department of Electrical & Computer Engineering, Johns Hopkins University, Baltimore, MD, USA
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2004

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Abstract

This paper presents a complete Single-chip Stereo Imager (SSI), incorporating two 128 × 128 pixel current-mode imagers and current-mode analog computation circuitry on a single integrated circuit. A modified version of block matching is used to find the stereo disparity at each location in the field of view. At each location, the sum-of-absolute-difference is computed, in parallel, for each possible disparity. The SSI is capable of operation at 66.1 million checked disparities per second (41 fps) while drawing 15.2 mA from a 5 V supply, including imagers and computation circuits. The SSI occupies 4.23 × 4.23 mm2 of area in a 0.5 μm (λ = 0.35 μm) 5 V, 3-metal, 2-poly CMOS process.