Analog VLSI and neural systems
Analog VLSI and neural systems
Wiring considerations in analog VLSI systems, with application to field-programmable networks
Wiring considerations in analog VLSI systems, with application to field-programmable networks
Communicating neuronal ensembles between neuromorphic chips
Neuromorphic systems engineering
An Analog VLSI System for Stereoscopic Vision
An Analog VLSI System for Stereoscopic Vision
Analogue Neural VLSI: A Pulse Stream Approach
Analogue Neural VLSI: A Pulse Stream Approach
The Retinomorphic Approach: Pixel-Parallel Adaptive Amplification,Filtering, and Quantization
Analog Integrated Circuits and Signal Processing
Multi-Chip Neuromorphic Motion Processing
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
A Modular Multi-Chip Neuromorphic Architecture for Real-Time Visual Motion Processing
Analog Integrated Circuits and Signal Processing
On the Performance of Pulsed and Spiking Neurons
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing
Multi-Chip Neuromorphic Motion Processing
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Retinomorphic Chips that see Quadrupple Images
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
High fill-factor imagers for neuromorphic processing enabled by floating-gate circuits
EURASIP Journal on Applied Signal Processing
Multi-chip implementation of a biomimetic VLSI vision sensor based on the Adelson-Bergen algorithm
ICANN/ICONIP'03 Proceedings of the 2003 joint international conference on Artificial neural networks and neural information processing
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I present a scalable 2-D address-event transmitter interface designed to take advantage of the high integration densities available with advanced submicron technology. To sustain throughput, it exploits the linear increase in the number of active neurons per row with array size, instead of counting on a linear increase in the unit-current/unit-capacitance ratio, as existing designs do. I synthesize an asynchronous implementation starting from a high-level specification, and present test results from a 104 x 96-neuron chip fabricated in a 1.2um CMOS process. Reading out the state of all neurons in a selected row in parallel, and sending their spikes in a tight burst of events, yields cycle times between 40 to 70ns---a substantial improvement over the 420ns minimum cycle time reported in earlier work.