Communications of the ACM
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The ASIC based self-timed systems use custom cells, which are not commercially available to the design community. Hence, Asynchronous self-timed designs have been a concept restricted to certain organizations around the world, which can afford the cost and effort. In order to make the methodology widely available it should be possible to build these systems using basic components available to the entire design community. In this dissertation work the focus will be on building a self-timed system using components available in a basic Xilinx FPGA, which is the most widely used FPGA in the world. The flow will be based on designing basic macro modules, which are consistent in timing in themselves and building bigger designs using such macro modules. At the end of the dissertation work a set of guidelines and design flow will be available to the design community to design self-timed systems using FPGAs. An example design of an arbitration based memory access module is given to illustrate the credibility and desirability of the methodology. It is part of a complex design in a larger chip and was a nightmare to meet the 125 MHz timing in Xilinx Virtex FPGA. Also it has some performance bottlenecks in terms of giving the required throughput. The self-timed design will be used to show that the design will exceedingly meet both the timing requirement and the performance requirement in the same FPGA.