Communications of the ACM
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Structured hardware compilation of parallel programs
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
Syntactic control of interference revisited
Theoretical Computer Science - Special issue on mathematical foundations of programming semantics
Syntactic control of interference
POPL '78 Proceedings of the 5th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Syntactic Control of Inference, Part 2
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
Compiling Application-Specific Hardware
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Type Reconstruction for Syntactic Control of Interference, Part 2
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Syntactic control of concurrency
Theoretical Computer Science - Automata, languages and programming: Logic and semantics (ICALP-B 2004)
Geometry of synthesis: a structured approach to VLSI design
Proceedings of the 34th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Full Abstraction Without Synchronization Primitives
Electronic Notes in Theoretical Computer Science (ENTCS)
Geometry of Synthesis II: From Games to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
On the compositionality of round abstraction
CONCUR'10 Proceedings of the 21st international conference on Concurrency theory
Compositional model extraction for higher-order concurrent programs
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Synchronous game semantics via round abstraction
FOSSACS'11/ETAPS'11 Proceedings of the 14th international conference on Foundations of software science and computational structures: part of the joint European conferences on theory and practice of software
Geometry of synthesis iv: compiling affine recursion into static hardware
Proceedings of the 16th ACM SIGPLAN international conference on Functional programming
The geometry of synthesis: how to make hardware out of software (abstract)
MPC'12 Proceedings of the 11th international conference on Mathematics of Program Construction
POPL '13 Proceedings of the 40th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
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Geometry of Synthesis is a technique for compiling higher-level programming languages into digital circuits via their game semantic model. Ghica (2007) first presented the key idea, then Ghica and Smith (2010) gave a provably correct compiler into asynchronous circuits for Syntactic Control of Interference (SCI), an affine-typed version of Reynolds's Idealized Algol. Affine typing has the dual benefits of ruling out race conditions through the type system and having a finite-state game-semantic model for any term, which leads to a natural circuit representation and simpler correctness proofs. In this paper we go beyond SCI to full Idealized Algol, enhanced with shared-memory concurrency and semaphores. Compiling ICA proceeds in three stages. First, an intermediate type system called Syntactic Control of Concurrency (SCC), is used to statically determine "concurrency bounds" on all identifiers in the program. Then, a program transformation called serialization is applied to the program to translate it into an equivalent SCC program in which all concurrency bounds are set to the unit. Finally, the resulting program can be then compiled into asynchronous circuits using a slightly enhanced version of the GoS II compiler, which can handle assignable variables used in non-sequential contexts.