Communications of the ACM
Integration, the VLSI Journal
High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Delay Insensitivity Does Not Mean Slope Insensitivity!
ASYNC '10 Proceedings of the 2010 IEEE Symposium on Asynchronous Circuits and Systems
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Self-timed circuits are slope sensitive: when the voltage of one input or internal node changes too slowly, the interconnected logical blocks might loose their local one-to-one synchronization. This phenomenon often leads to unwanted global dead-locks of the entire circuit. The deep-submicronic manufacturing process mismatches might create such situations where one logical block is significantly slower than the others. We applied two known solutions for ensuring the correct Celement behavior whatever the slopes are: the transistors are resized and the supply voltage is reduced in order to guarantee the overall chip correctness taking into account the process variations.