An asynchronous architecture for modeling intersegmental neural communication

Authors:
Girish N. Patel;Michael S. Reid;David E. Schimmel;Stephen P. DeWeerth
Affiliations:
Georgia Institute of Technology, Atlanta, GA;Georgia Institute of Technology, Atlanta, GA;Georgia Institute of Technology, Atlanta, GA;Georgia Institute of Technology, Atlanta, GA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

Citing 7
Cited 0

Micropipelines

Communications of the ACM
Analog VLSI and neural systems

Analog VLSI and neural systems
VLSI analogs of neuronal visual processing: a synthesis of form and function

VLSI analogs of neuronal visual processing: a synthesis of form and function
Communicating neuronal ensembles between neuromorphic chips

Neuromorphic systems engineering
Tomorrow's Digital Hardware will be Asynchronous and Verified

Proceedings of the IFIP 12th World Computer Congress on Algorithms, Software, Architecture - Information Processing '92, Volume 1 - Volume I
A VLSI Architecture for Modeling Intersegmental Coordination

ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Synthesis of Asynchronous VLSI Circuits

Synthesis of Asynchronous VLSI Circuits

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an asynchronous VLSI architecture for modeling the oscillatory patterns seen in segmented biological systems. The architecture emulates the intersegmental synaptic connectivity observed in these biological systems. The communications network uses address-event representation (AER), a common neuromorphic protocol for data transmission. The asynchronous circuits are synthesized using communicating hardware processes (CHP) procedures. The architecture is scalable, supports multichip communication, and operates independent of the type of silicon neuron (spiking or burst envelopes). A 16-segment prototype system was developed, tested, and implemented; data from this system are presented.