Pausible clocking-based heterogeneous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bioinformatics: A Biologist's Guide to Biocomputing and the Internet
Bioinformatics: A Biologist's Guide to Biocomputing and the Internet
ARM System-on-Chip Architecture
ARM System-on-Chip Architecture
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
A multiple-clock-domain bus architecture using asynchronous fifos as elastic elements
A multiple-clock-domain bus architecture using asynchronous fifos as elastic elements
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A single-chip shared-memory multiprocessor architecture is introduced which is particularly well suited to common bioinformatic computing tasks. The architecture uses asynchronous bus interfaces to create an integrated circuit design methodology allowing for scaling of the multiprocessor with very little design effort. A key aspect of this design methodology is that it is not necessary to expend significant design resources and chip area on the clock tree. An analysis of the Smith-Waterman alignment algorithm running on this architecture shows that the performance penalty due to increased bus latency compared to a fully synchronous architecture is negligible.